The present invention generally relates to the design of electronic circuits such as semiconductor integrated circuit (IC) devices and printed circuit boards. Particularly, the present invention relates to a method, a tool and a computer program product for creating a layout for an electronic circuit.
An IC layout is the representation of an IC in terms of planar geometric shapes that correspond to patterns of shapes actually drawn on photo masks used in semiconductor device fabrication. A printed circuit board, hereinafter called board, consists of “printed wires” attached to a sheet of insulator. A board layout is the representation of a board in terms of planar geometric shapes that correspond to pattern of shapes actually drawn of photo masks used in the board device fabrication.
Optimal layouts cannot be found in a reasonable time. Even simplified versions of the problem have been proved to be NP-complete or NP-hard according to the computational complexity theory. In practice, the layout problem is broken up into several phases such as floorplanning, placement, and routing. With the large sizes of modern board and IC designs, the phases are usually performed with automatic or semi-automatic electronic design automation tools.
Floorplanning is a preparatory step of creating an IC die map showing the expected locations for various elements of the IC. Placement and routing, also called place and route, are similar at a high-level for both ICs and boards, but the actual details are very different. During place and route board components (blocks) are placed on a board design and the wires are drawn between them and for ICs a layout of a larger block of the IC or the whole IC is created from layouts of smaller sub-blocks. The type of blocks and the actual place and route process itself depends on design methodology.
Due to its complexity the place and route process is usually performed in two separate stages: placement, i.e., determining the positions of the sub-blocks in the design area, and routing, i.e., interconnecting the sub-blocks while keeping the positions of the sub-blocks. Placement is considered as the most important phase of the IC layout design because of its difficulty. The result of the placement directly affects IC area, routeability, and performance. However, also the importance of routing is increasing continuously.
There are three basic styles of routing tools on the market: grid-based routers, shape-based routers, and graph-based routers. A grid-based router superimposes a mesh-like template over the routing area of design with evenly spaced tracks, all grids, running both vertically and horizontally across the design area. Any routing operation that is performed must be cognizant of all the grid points as a whole. A shape-based router in contrast does not need such a grid. A graph-based router views a design similarly to a grid-based router in that there are both vertical and horizontal grids that can be followed, but it only considers these grids as a guideline for routing and is not mandated to use them.
The blocks and sub-blocks that form an IC or a board can be divided in different hierarchy levels: the device level comprising elements such as transistors, diodes, and capacitors, the book level comprising elements from a library such as gates (i.e. NAND and NOR circuits) and latches, the macro level comprising complex elements like adders and dividers, the unit level comprising elements from the macro level (i.e. adder) and the chip level comprising elements from the macro and the unit level (i.e. Floating Point Unit), and the board level comprising elements such as ICs.
Both placement and routing are usually performed incrementally. In an iteration step the layout is optimised for various goals while ensuring signal integrity and compliance to various design rules related to the semiconductor manufacturing process. Examples for placement optimisation goals are minimizing the wire-length between the various blocks as the signal delay increases with the wire length, and maximising the wire density to save chip area. Examples for routing optimisation goals are minimizing the wire length, and having the same or similar length for certain wires. If it is not possible to achieve the optimisation goals then the current layout is dropped, the design of the IC will be changed and the placement and routing process is started again.
With the enduring trend of devices (e.g. transistors) and books and macros (e.g. gates) becoming smaller and faster, IC designs are being limited by the delays of the wires connecting the devices and macros rather than by their area. For example, for semiconductor process geometries in the 130 nm range it is reported that wires account for nearly 75% of an IC's overall delay. And nearly 40% of the wires can attribute more than 50% of their total wire capacitance to the cross coupling between neighbouring wires. At smaller geometries (e.g. in toady's 90 nm range), the situation is becoming even more severe.
Another limiting factor for IC designs is the wiring density. As the devices become smaller the wires do not scale to the same amount. The density of the IC is therefore more and more limited by the wiring density and not by the density of the devices. It is necessary to increase the space between the devices to be able to route the IC.
Traditional design methodologies do not consider wire delays and capacitance until after placement since routing is performed after placement at the end of the design flow. Designers must iterate multiple times in hope of achieving design closure. And often, in order to meet a strict schedule for the IC release to manufacturing, designers are forced to accept a lower performing IC or the risk of potential failures due to unresolved signal integrity issues.